sibsutisВестник СибГУТИThe Herald of the Siberian State University of Telecommunications and Information Science1998-6920СибГУТИsibsutis-177Research ArticleСтатьиСхемотехника КМОП полных сумматоровCMOS Full-Adder SchematicsШубинВ. В.ShubinV. V.shubin@nzpp.ruАО «НЗПП с ОКБ»; СибГУТИRussian Federation201624102022022537Copyright © Шубин В.В., 20222022Шубин В.В.Shubin V.V.Данная работа распространяется под лицензией Creative Commons Attribution 4.0.This work is licensed under a Creative Commons Attribution 4.0 License.https://vestnik.sibsutis.ru/jour/article/view/177

В работе описаны принципы построения схемотехники ячейки полного КМОП сумматора. Приведены наиболее распространённые конструктивные решения различных стилей проектирования, описаны их достоинства и недостатки. Представлены результаты моделирования и сравнения описанных решений. Кроме того, предложено решение ячейки сумматора, которое обладает превосходящими характеристиками по быстродействию по формированию сигнала переноса в сравнении с известными сумматорами и, следовательно, позволяет добиться более высокого быстродействия при построении многоразрядных сумматоров.

In this paper, the base rules of CMOS full-adder cell’s circuit technology are described. The most widespread of the constructive solutions in different design styles, their merits and disadvantages are investigated. The results of the simulation and comparison of the described solutions are presented. In addition, a new decision of the CMOS adder cell is proposed. This adder has superior speed characteristics of carry signal shaping while constructing multibit adders.

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The authors declare that there are no conflicts of interest present.