<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE article PUBLIC "-//NLM//DTD JATS (Z39.96) Journal Publishing DTD v1.3 20210610//EN" "JATS-journalpublishing1-3.dtd">
<article article-type="research-article" dtd-version="1.3" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xml:lang="ru"><front><journal-meta><journal-id journal-id-type="publisher-id">sibsutis</journal-id><journal-title-group><journal-title xml:lang="ru">Вестник СибГУТИ</journal-title><trans-title-group xml:lang="en"><trans-title>The Herald of the Siberian State University of Telecommunications and Information Science</trans-title></trans-title-group></journal-title-group><issn pub-type="ppub">1998-6920</issn><publisher><publisher-name>СибГУТИ</publisher-name></publisher></journal-meta><article-meta><article-id pub-id-type="doi">10.55648/1998-6920-2023-17-2-69-83</article-id><article-id custom-type="elpub" pub-id-type="custom">sibsutis-759</article-id><article-categories><subj-group subj-group-type="heading"><subject>Research Article</subject></subj-group><subj-group subj-group-type="section-heading" xml:lang="ru"><subject>Статьи</subject></subj-group></article-categories><title-group><article-title>Отказы интегральных схем, вызванные пробоем диэлектрика</article-title><trans-title-group xml:lang="en"><trans-title>Failures of ICs Caused by Dielectric Breakdown</trans-title></trans-title-group></title-group><contrib-group><contrib contrib-type="author" corresp="yes"><contrib-id contrib-id-type="orcid">https://orcid.org/0000-0002-2974-0497</contrib-id><name-alternatives><name name-style="eastern" xml:lang="ru"><surname>Шубин</surname><given-names>В. В.</given-names></name><name name-style="western" xml:lang="en"><surname>Shubin</surname><given-names>V. V.</given-names></name></name-alternatives><bio xml:lang="ru"><p>Шубин Владимир Владимирович, к.т.н., доцент кафедры технической электроники СибГУТИ, начальник отдела по разработке аналоговых ИМС АО «НЗПП Восток»</p><p>630082, Новосибирск, ул. Дачная, 60</p></bio><bio xml:lang="en"><p>Vladimir V. Shubin, Cand. of Sci. (Engineering), assistant professor of the Department of Technical Electronics of Sib-SUTIS, Head of the Development of analog ICs of JSC "NZPP Vostok department"</p><p>630082, Novosibirsk, Dachnaya str., 60</p></bio><email xlink:type="simple">shubin@nzpp.ru</email><xref ref-type="aff" rid="aff-1"/></contrib></contrib-group><aff-alternatives id="aff-1"><aff xml:lang="ru"><institution>Сибирский гос. унив. телекоммуникаций и информатики (СибГУТИ)</institution><country>Россия</country></aff><aff xml:lang="en"><institution>Siberian State University of Telecommunications and Information Science (SibSUTIS)</institution><country>Russian Federation</country></aff></aff-alternatives><pub-date pub-type="collection"><year>2023</year></pub-date><pub-date pub-type="epub"><day>02</day><month>04</month><year>2023</year></pub-date><volume>17</volume><issue>2</issue><fpage>69</fpage><lpage>83</lpage><permissions><copyright-statement>Copyright &amp;#x00A9; Шубин В.В., 2023</copyright-statement><copyright-year>2023</copyright-year><copyright-holder xml:lang="ru">Шубин В.В.</copyright-holder><copyright-holder xml:lang="en">Shubin V.V.</copyright-holder><license xml:lang="ru" license-type="creative-commons-attribution" xlink:href="https://creativecommons.org/licenses/by/4.0/" xlink:type="simple"><license-p>Данная работа распространяется под лицензией Creative Commons Attribution 4.0.</license-p></license><license xml:lang="en" license-type="creative-commons-attribution" xlink:href="https://creativecommons.org/licenses/by/4.0/" xlink:type="simple"><license-p>This work is licensed under a Creative Commons Attribution 4.0 License.</license-p></license></permissions><self-uri xlink:href="https://vestnik.sibsutis.ru/jour/article/view/759">https://vestnik.sibsutis.ru/jour/article/view/759</self-uri><abstract><p>В статье описаны некоторые проблемы отказов в работе интегральных схем (ИС) и их предотвращение конструктивно-технологическими и схемо-топологическими способами. Рассмотрены, обобщены и систематизированы вопросы, связанные с проблемами отказов ИС, вызванных пробоем диэлектрика. Представлены некоторые примеры, которые могут быть использованы в практической деятельности при разработке ИС для повышения их надёжности на ранних этапах проектирования с учётом современных тенденций развития в области микроэлектроники.</p></abstract><trans-abstract xml:lang="en"><p>The paper describes some problems of operation failures of integrated circuits (ICs) and corresponding preventative measures by constructive-technological, schematic-topological methods at the early stages of design process. The issues related to the problems of IC failures caused by dielectric breakdown are considered, generalized and systematized. Some examples that can be used in practice when developing ICs to improve their reliability, taking into account current trends in the microelectronics field.</p></trans-abstract><kwd-group xml:lang="ru"><kwd>пробой диэлектрика</kwd><kwd>электростатический разряд</kwd></kwd-group><kwd-group xml:lang="en"><kwd>dielectric breakdown</kwd><kwd>electrostatic discharge</kwd></kwd-group></article-meta></front><back><ref-list><title>References</title><ref id="cit1"><label>1</label><citation-alternatives><mixed-citation xml:lang="ru">DiStefano T. H., Shatzkes M. Impact ionization model for dielectric instability and breakdown // Appl. Phys. Lett. 1974. V. 25. P. 685–687.</mixed-citation><mixed-citation xml:lang="en">DiStefano T. H., Shatzkes M. Impact ionization model for dielectric instability and breakdown // Appl. Phys. Lett. 1974. V. 25. P. 685–687.</mixed-citation></citation-alternatives></ref><ref id="cit2"><label>2</label><citation-alternatives><mixed-citation xml:lang="ru">Solomon P. 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