Layout Design Features of Differential Pairs and Current Mirrors of Complex Functional Blocks of Submicron Integrated Circuits like SOC

Abstract

This paper considers main causes of element mismatch in differential pairs and current mirrors while designing complex functional (CF) blocks of digital-to-analog and analog-to-digital converters of integrated circuits according to submicron CMOS technology. Main problems encountered while designing differential pairs and current mirrors being part of CF blocks and using fictitious (dummy) transistors are considered. General principles of mismatched elements layout are presented. The necessity of using dummy transistors being part of differential pairs and current mirrors is presented. The analysis of mismatched elements layout design using dummy elements is conducted. Basic dummy transistor connection variants are given. Check code of dummy transistors connection for various differential pairs design and current mirrors by means of Calibre topology verification by Mentor Graphics.