Digital filters workflow simulation of high speed modulator for PLC modems
Abstract
Digital filters models of quadrature modulator for data transmission via power circuits are developed. The filter is optimized according to electrical parameters for reduction of energy consumption and VLSI amount.
About the Authors
A. V. Gluhov
ОКБ ОАО «НЗПП с ОБК»
Russian Federation
Russian Federation
A. A. Alekseev
ФГОБУ Сибирского государственного университета телекоммуникаций и информатики
Russian Federation
Russian Federation
G. V. Perov
ОКБ ОАО «НЗПП с ОБК»
Russian Federation
Russian Federation
V. I. Sedinin
ФГОБУ Сибирского государственного университета телекоммуникаций и информатики
Russian Federation
Russian Federation
References
1. Markovic D., Nikolic B., Brodersen R.W., Power and Area Efficient VLSI Architectures for Communication Signal Processing//Berkley Wireless Research Center, University of California at Berkley. Browse Conference Publications > Communications, 2006. ICC '06 P.54-81.
2. Hogenauer E.B. An Economical Class of Digital Filters for Decimation and Interpolation// IEEE Transitions on acoustics, speech, and signal processing, vol. ASSP-29,Nо.2, April 1981.P 155-162.
3. Altera application note AN455. Understanding CIC Compensation Filter, Аpril, 2007, P.1-17.
4. Ryan Kastner, Anup Hosangadi and Farzan Fallah, Arithmetic Optimization Techniques for Hardware and Software Design, Cambridge University Pres, 2010, P.35-67.
Review
For citations:
Gluhov A.V., Alekseev A.A., Perov G.V., Sedinin V.I. Digital filters workflow simulation of high speed modulator for PLC modems. The Herald of the Siberian State University of Telecommunications and Information Science. 2013;(3):78-83. (In Russ.)
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