Designing of Complex-Functional Blocks of Mixed Signal on the Basis of Sub-Micron Technology Illustrated by Videoencoder Micro-Chip. Part 2. "Silicon" Microchip Verification

Abstract

A three-channel multi-standard PAL/NTSC mixed-signal video encoder IP core for digital TV and multimedia applications has been designed. The IP core has been manufactured using a standard 0.18 µm CMOS technology flow with analog options. In the second part of the paper, results of the IP core investigation are presented. A few chip scanning electron microscopy cross-sectional images are presented. Total power dissipation has been measured to be 89 mW. Measured DAC parameters show 10 bit 27 MHz performance. The measured integral nonlinearity and differential nonlinearity are ±0.7 LSB and ±0.35 LSB, respectively. This chip design can be used from digital to analog video encoding either separately, or as an IP core. Range of application of this integrated circuit is from consumer digital TV to a security applications and some special uses.