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Failures of ICs Caused by Dielectric Breakdown

https://doi.org/10.55648/1998-6920-2023-17-2-69-83

Abstract

The paper describes some problems of operation failures of integrated circuits (ICs) and corresponding preventative measures by constructive-technological, schematic-topological methods at the early stages of design process. The issues related to the problems of IC failures caused by dielectric breakdown are considered, generalized and systematized. Some examples that can be used in practice when developing ICs to improve their reliability, taking into account current trends in the microelectronics field.

About the Author

V. V. Shubin
Siberian State University of Telecommunications and Information Science (SibSUTIS)
Russian Federation

Vladimir V. Shubin, Cand. of Sci. (Engineering), assistant professor of the Department of Technical Electronics of Sib-SUTIS, Head of the Development of analog ICs of JSC "NZPP Vostok department"

630082, Novosibirsk, Dachnaya str., 60



References

1. DiStefano T. H., Shatzkes M. Impact ionization model for dielectric instability and breakdown // Appl. Phys. Lett. 1974. V. 25. P. 685–687.

2. Solomon P. Breakdown in silicon oxide – a review // J. Vac. Sci. Technol. 1977. V. 14. P. 1122–1130.

3. Klein N. Electrical breakdown mechanisms in thin insulators // Thin Solid Films. 1978. V. 50. P. 223–232.

4. Yeo Y. C., King T. J., Hu C. MOSFET Gate Leakage Modeling and Selection Guide for Alternative Gate Dielectrics Based on Leakage Considerations // IEEE Transactions on Electron Devices. 2003. V. 50, № 4. P. 1027–1035.

5. Hastings A. The Art of Analog Layout. New Jersey: Pearson Prentice Hall, 2006. 648 p. 6. Fowler R. H., Nordheim L. Electron emission in intense electric fields // Proc. R. Soc. London, Ser. A. 1928. V. 119. P. 173–181.

6. Larcher L., Passagnella A., Ghidman G. A Model of the Stress Induced Leakage Current in Gate Oxides // IEEE Trans. Electron Devices. 2001. V. 48, № 2. P. 285–288.

7. Lenahan P. M., Mele J. J., Campbell J. P., Kang A. Y., Lowry R. K., Woodbury D., et al. Direct Experimental Evidence Linking Silicon Dangling Bond Defects to oxide Leakage Currents // Proc. International Reliability Physics Symp. 2001. P. 150–155.

8. Yavorskii, B. M. Spravochnik po fizike dlya inzhenerov i studentov VUZov [Handbook of Physics for engineers and university students]. 8th ed., Moscow: Onyx; World and Education, 2006. p.1056.

9. Ker Ming-Dou, Yuan-Wen Hsiao. CDM ESD Protection in CMOS Integrated Circuits // Proc. The Argentine School of Micro-Nanoelectronics, Technology and Applications, 2008. P. 61–65.

10. Henry L., Barth J., Hyatt H., at al. Charged device model metrology: limitations and problems // Microelectron. Reliab. Jun. 2002. V. 42, № 6. P. 919–927.

11. Dabral S., Maloney T. J. Basic ESD and I/O Design. Toronto: John Wiley & Sons Inc. 1998. V. XIII. 328 p.

12. Chen J. Z., Amerasekera A., Duvvury Ch. Design Methodology for Optimizing Gate Driven ESD Protection Circuits in Submicron CMOS Processes // Proc. EOS/ESD Symp., 1997. P. 1–10.

13. Richier C., Salome P., Mabboux G., at al. Investigation on different ESD protection strategies devoted to 3.3 V RF applications (2 GHz) in a 0.18 m CMOS process // Proc. EOS/ESD Symp., Sep. 2000. P. 251–259.

14. Clein D. CMOS IC LAYOUT. Concepts, methodologies and tools. Boston: Newnes. 2000. № XV. 261 p.

15. Razavi B. Design of Analog CMOS Integrated Circuits. McGraw-Hill Education. NY, 2017. 782 p.


Review

For citations:


Shubin V.V. Failures of ICs Caused by Dielectric Breakdown. The Herald of the Siberian State University of Telecommunications and Information Science. 2023;17(2):69-83. (In Russ.) https://doi.org/10.55648/1998-6920-2023-17-2-69-83

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ISSN 1998-6920 (Print)